FIG. 1 illustrates a conventional regulator for converting a variable DC input voltage (VIN) ranging, for example, from 7V to 40V, into a DC output voltage (VOUT) of, for example, 5V. The conventional regulator includes a reference voltage generation module 1′ that is operable to generate a first reference voltage output (Vrf1) and a second reference voltage (Vrf2) based on the DC input voltage (VIN), and a conversion module 5′ that is coupled to the reference voltage generation module 1′ and that is operable to generate the DC output voltage (VOUT) based on the DC input voltage (VIN), on the first reference voltage output (Vrf1) and on the second reference voltage (Vrf2) from the reference voltage generation module 1′.
Referring further to FIG. 2A, the reference voltage generation module 1′ has an input terminal (P1) for receiving the DC input voltage (VIN), and includes first to sixth transistors 11-16 and a resistor 17. The first, fourth and fifth transistors 11, 14, 15 are PMOS transistors, and the second, third and sixth transistors 12, 13, 16 are NMOS transistors. The first to third transistors 11, 12, 13 are coupled sequentially in series between the input terminal (P1) and ground. The fourth to sixth transistors 14, 15, 16 and the resistor 17 are coupled sequentially in series between the input terminal (P1) and ground. Sources of the first and fourth transistors 11, 14 are coupled to the input terminal (P1). Gates of the first and fourth transistors 11, 14, drain of the fourth transistor 14 and source of the fifth transistor 15 are coupled to each other. Drains of the first and second transistors 11, 12 and gate of the second transistor 12 are coupled to each other. A source of the second transistor 12, a drain of the third transistor 13, and gates of the third and sixth transistors 13, 16 are coupled to each other. A gate and a drain of the fifth transistor 15, and a drain of the sixth transistor 16 are coupled to each other. Sources of the third and sixth transistors 13, 16 are coupled respectively to ground and one end of the resistor 17. The other end of the resistor 17 is coupled to ground. The potential at a common node (P2) among the gate of the first transistor 11, the gate and drain of the fourth transistor 14 and the source of the fifth transistor 15 serves as a first voltage (V1). The potential at a common node (P3) among the gate and drain of the fifth transistor 15 and the drain of the sixth transistor 16 serves as a second voltage (V2). The potential at a common node (P4) between the gate and drain of the second transistor 12 serves as a third voltage (V3). The potential at a common node (P5) among the gate and drain of the third transistor 13 and the gate of the sixth transistor 16 serves as the second reference voltage (Vrf2). The first, second and third voltages (V1, V2, V3) cooperatively constitute the first reference voltage output (Vrf1).
Referring to FIG. 2B, the conversion module 5′ includes an error amplifier circuit 51, and a voltage division circuit 52 coupled to the error amplifier circuit 51.
The error amplifier circuit 51 receives the first to third voltages (V1, V2, V3) (i.e., the first reference voltage output (Vrf1)) and the second reference voltage (Vrf2) from the reference voltage generation module 1′. The error amplifier circuit 51 is operable to generate an amplified signal (As) based on the first to third voltages (V1, V2, V3), on the second reference voltage (Vrf2) and on a divided voltage (Vd) associated with the DC output voltage (VOUT). The error amplifier circuit 51 includes a first transistor 511, a differential pair 50 of second and third transistors 512, 513, fourth and fifth transistors 514, 515, and first to eighth bias transistors 531-538. The transistors 511, 512, 513, 531, 532, 535, 536 are PMOS transistors, and the transistors 514, 515, 533, 534, 537, 538 are NMOS transistors. Each of the first to fifth transistors 511-515 and the first to eight bias transistors 531-538 has a source, drain and gate that serve respectively as a first terminal, a second terminal and a control terminal. The source and gate of the first transistor 511 receive respectively the DC input voltage (VIN) and the first voltage (V1) (from the common node (P2) of the reference voltage generation module 1′ (FIG. 2A)). The drain of the first transistor 511 and the sources of the second and third transistors 512, 513 are coupled to each other. The gates of the second and third transistors 512, 513 receive respectively the divided voltage (Vd) and the second reference voltage (Vrf2) (from the common node (P5) of the reference voltage generation module 1′ (FIG. 2A)). The drain of the second transistor 512, and the drain and gate of the fourth transistor 514 are coupled to each other. The drain of the third transistor 513, and the drain and gate of the fifth transistor 515 are coupled to each other. The sources of the fourth and fifth transistors 514, 515 are coupled to ground. The first to fourth bias transistors 531, 532, 533, 534 are coupled sequentially in series between the source of the first transistor 511 and ground. The fifth to eighth bias transistors 535, 536, 537, 538 are coupled sequentially in series between the source of the first transistor 511 and ground. The sources of the first and fifth bias transistors 531, 535 are coupled to the source of the first transistor 511, thereby receiving the DC input voltage (VIN). The drain of the first bias transistor 531 is coupled to the source of the second bias transistor 532. The gates of the first and fifth bias transistors 531, 535, and the drains of the second and third bias transistors 532, 533 are coupled to each other at a first common node (n1). The gates of the second and sixth bias transistors 532, 536 are coupled to each other for receiving the second voltage (V2) from the common node (P3) of the reference voltage generation module 1′ (FIG. 2A). The gates of the third and seventh bias transistors 533, 537 are coupled to each other for receiving the third voltage (V3) from the common node (P4) of the reference voltage generation module 1′ (FIG. 2A). The drain, source and gate of the fourth bias transistor 534 are coupled respectively to the source of the third bias transistor 533, ground and the drain of the third transistor 513. The drain of the fifth bias transistor 535 is coupled to the source of the sixth bias transistor 536. The drains of the sixth and seventh bias transistors 536, 537 are coupled to each other at a second common node (n2). The drain, source and gate of the eighth bias transistor 538 are coupled respectively to the source of the seventh bias transistor 537, ground and drain of the second transistor 512.
Thus, the first to third transistors 511, 512, 513 are operable to be conducting or non-conducting in response, respectively, to the first voltage (V1), the divided voltage (Vd) and the second reference voltage (Vrf2). The second and sixth bias transistors 532, 536 are operable to be conducting or non-conducting in response to the second voltage (V2). The third and seventh bias transistors 533, 537 are operable to be conducting or non-conducting in response to the third voltage (V3). The amplified signal (As) is outputted at the second common node (n2).
The voltage division circuit 52 receives the DC input voltage (VIN), and the amplified signal (As) from the second common node (n2) of the error amplifier circuit 51. The voltage division circuit 52 is operable to generate, based on the DC input voltage (VIN) and the amplified signal (As), the DC output voltage (VOUT) and the divided voltage (Vd). The voltage division circuit 52 includes a sixth transistor 521, and first to third resistors 522, 523, 524 coupled sequentially in series between the sixth transistor 521 and ground. The sixth transistor 521 is a PMOS transistor that has a source for receiving the DC input voltage (VIN), a gate coupled to the second common node (n2) for receiving the amplified signal (As) therefrom, and a drain coupled to one end of the first resistor 522. When the sixth transistor 521 conducts in response to the amplified signal (As), a voltage across the first to third resistors 522, 523, 524 is outputted to serve as the DC output voltage (VOUT), and a voltage across the third resistor 524 is outputted to serve as the divided voltage (Vd).
In such a configuration, as the DC input voltage (VIN) initially increases from zero, the second reference voltage (Vrf2) outputted at the common node (P5) of the reference voltage generation module 1′ increases until reaching a gate-to-source voltage of the third transistor 13. Thereafter, the second reference voltage (Vrf2) remains unchanged and is thus insensitive to the increase of the DC input voltage (VIN). As a result, the conventional regulator may not output the DC output voltage (VOUT) in a stable way after the second reference voltage (Vrf2) reaches the gate-to-source voltage of the third transistor 13.